Field Effect Transistor (FET) technology has reached nanoscale dimensions. This has an impact on their operation, performance and reliability. Analytical formulae are no longer able to describe the operation of these devices, thus Technology Computer Aided Design (TCAD) has become essential to predict the operation and performance of these miniature devices.
The purpose of the module is to understand the impact of very short channel lengths on the performance of FETs. Currently, channel lengths are in the 10 nm range and research is pushing this to even smaller dimensions – 2D and 1D FETs. The proximity of the drain to the source seriously undermines the control of the gate and different techniques need to be applied to maintain the FETs characteristics at the nanoscale.
Industry is increasingly relying on software packages to solve the carrier transport equations numerically. We will use one of these packages, Sentaurus developed by Synopsis, to investigate the problems associated with nanoscale FETs.
We will evaluate the most recent FETs in research and development, covering topics such as finFETs, Ultra thin body and box FETs, nanowire and nanosheet FETs.
At the end of this module you will understand the current state-of-the-art of nanoFETs, their strengths and weaknesses as well as being able to use a commercial tool - Sentaurus - to simulate the performance of novel nanoscale semiconductor devices.

At the end of this module, you will be able to:
1. Critically analyse transport processes in nanoscale FETs, including self-heating effects, that have become important in nanowire and nanosheet FETs.
2. Derive device characteristics given the geometry and material parameters using numerical simulations in Sentaurus TCAD.
3. Extract the performance parameters of FETs and critically appraise their relevance in applications.
4. Read and write technical papers in the field of semiconductor device design and their impact on future CMOS developments.
5. Design/optimise current and novel devices using Sentaurus TCAD from Synopsis.

This module covers the challenges in moving to nanoscale FETs.
• Downscaling of FETs and how to maintain reliability
• Strain engineering in MOSFETs to increase the speed of electrons and holes
• Silicon on insulator (SOI) – partially, fully depleted and Ultra-Thin Body and BOX FETs.
• Decreased dimensionality FETs:
o finFETs (commercially available),
o nanowire and nanosheet FETs.
• Physical challenges such as self-heating.
• the necessity to design devices using TCAD (Technology Computer Aided Design) - Sentaurus