The aim of this modules is to enable you to design digital systems of medium complexity, and to teach you how to implement the design with FPGA/CPLD devices, memory devices and microprocessors. To enable you to design systems that obey timing constraints and are testable.

Upon successful completion of this module, you will be able to:

1. design complex, high speed digital systems
2. use some of the modern CAD tools to help with the design
3. implement such designs using programmable logic (e.g. FPGAs)
4. design with digital building blocks (such as memory chips, microprocessors, arithmetic circuits etc.)

In this module the principles and techniques for designing reasonably large digital circuits and systems will be studied. Based on the design of a practical medium-sized circuit, and a number of smaller examples, the module covers the following topics:
System bus interfacing;
FPGA architectures;
Multiplier circuits;
Dynamic memory interfacing and DMA control circuits;
Timing issues in digital circuits: hazards, metastability and races;
High-speed digital design techniques;
JTAG standard and design for testability.