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ELEC50010 Instruction Architectures and Compilers

Lecturer(s): Dr John Wickerson; Prof Peter Cheung


This module covers the compute stack from implementation using gates to emitting instructions. It builds further on your knowledge of computer architecture and introduces you to the theory and design of language processors and compilers. Computer architecture and digital electronics go hand in hand, as in the 1st year. Thus more complex digital electronics will be covered together with implementation hardware and verification software.

Learning Outcomes

Upon successful completion of this module, you will be able to:

1. Describe how high-level programs are executed through the sequencing of instructions
2. Create a compiler from a high-level language to an instruction-based language
3. Program a software functional model of a CPU or cache
4. Optimise high-level data structures to exploit the low-level memory hierarchy
5. Design data-structures which can represent programs
6. Determine the worst-case propagation delay of a combinational circuit
7. Design arithmetic circuits to meet a specification and determine the propagation delay
8. Evaluate possible architectural solutions against a set of performance objectives
9. Discuss the relationship between throughput, latency, and pipelining


- ISAs
- State machines
- Data and control path
- Critical paths and timing
- Pipelining
- Physical storage
- Arithmetic
- Buses
- RTL (Verilog)
- Memory Hierarchy
- Grammars
- Interpreters
- ASTs
Exam Duration: N/A
Coursework contribution: 60%

Term: Autumn & Spring

Closed or Open Book (end of year exam): N/A

Coursework Requirement:
         Laboratory Experiment
         Non-assessed problem sheets

Oral Exam Required (as final assessment): no

Prerequisite module(s): None required

Course Homepage: unavailable

Book List: