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ELEC70093 ADIC Laboratory Experiments

Lecturer(s): Prof Pantelis Georgiou


This lab aims to develop advanced skills in utilising industry-strength Electronic Design Automation (EDA) tools for microelectronic design. The lab comprises of four topics: Cadence IC Design (Analogue/Digital), Digital Design, Digital System Design and Silicon Reliability. Tools and design flows include the Cadence Design Systems (CDS) for full-custom analogue/mixed signal, and standard-cell digital, digital Systems on Chip (SoC) design using the latest toolflows from Xilinx, an FPGA vendor for practical skills in designing digital systems that include hardcore processors interfaced with FPGA logic.

Learning Outcomes

After completion of this lab, you will be able to:
1) Evaluate the issues associated with modern IC manufacture processes and the various testing methodologies.
2) Evaluate the full custom design flow for analogue and digital integrated circuits in CDS.
3) Recognise the essential features of programmable logic devices (FPGAs) and how they are built.
4) Use Verilog to design combinational and sequential circuits, applying the principles of digital hardware design on FPGAs.
5) Evaluate and analyse the issues associated with modern SoC systems and develop digital Systems-on-Chip using FPGAs through Xilinx’s toolflow.
6) Consider and justify communication protocols between the processor and an integrated IP and evaluate and model the design flow for integrating a VHDL and HLS based IP with the processor
7) Appreciation for the importance of functional safety, particularly in mission-critical systems and knowledge of error-mitigation hardware commonly found in modern CPUs and FPGAs
8) Ability to write hardware and software employing approaches that increase reliability.


1) Introduction to AMS 0.35um process
2) Simulation of PSRR, CMRR; Stability analysis
3) Noise analysis; Monte-Carlo analysis; Corner analysis
4) Periodic Steady State (PSS) analysis; Periodic AC (PAC) analysis
5) General guidelines for analogue layout; Perform post-extraction simulations

Digital Design Lab:
1) Introduction to integrated circuits and programmable logic devices (FPGAs).
2) Schematic hardware design versus textual hardware description languages.
3) Introduction to the Verilog language.
4) Moore and Mealy machines.
5) Designing finite state machines in Verilog.
6) Analogue-to-digital conversion and digital-to-analogue conversion.
7) Serial-to-parallel and parallel-to-serial interfaces.
8) Design of a voice echo synthesiser.

1) Synthesis digital circuitry with Cadence RC and Encounter 1) Introduction to the Zynq platform
2) Design of a SoC system to control the LEDs on the board (HW and SW)
3) Integration of an IP block to the SOC system
4) Create AXI4-lite interfaces

Silicon Reliability:
1) Self-driving car motivational example, functional safety, regulatory standards, security, fault modes, manufacturing defects, design-for-test
2) Single-event effects, radiation sources, radiation testing
3) Temporal/spatial redundancy/diversity, error-correcting codes, built-in self-test, watchdog timers
4) Synthesis gotchas, state machine encoding, FPGA features, common-mode failure, scrubbing, algorithm-based fault tolerance
5) Hands-on application build, analyse, harden, test and evaluate
Exam Duration: N/A
Exam contribution: 0%
Coursework contribution: 100%

Term: N/A

Closed or Open Book (end of year exam): N/A

Coursework Requirement:
         Coursework only module

Oral Exam Required (as final assessment): N/A

Prerequisite module(s): None required

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