To enable the student to analyse and synthesize small synchronous digital systems.
To give an understanding of the factors that limit the performance of digital systems.
To give an understanding of how digital systems communicate with each other and with their external environment.

Students should be able to:
* analyse the operation of synchronous digital systems
* synthesize a synchronous digital system to meet a specification
* determine the worst-case propagation delay of a combinational circuit
* evaluate the performance of A/D and D/A conversion circuits
* design arithmetic circuits to meet a specification and determine the propagation delay

IEC617 dependency notation. Interfacing techniques for digital systems: synchronous bit-serial transmission; timing constraints arising from setup and hold times; static RAM memories, microprocessor-to-memrory interfacing. Sequencing circutry using shfit registers and counters; analysis and design of synchronous state machines; timing constraints and glitches. Data conversion: D/A converters for signed and unsigned numbers, current switched R-2R ladder, output deglitching. Flash and successive approximation A/D converters. Dither. Sample/hold circuits. Performance criteria for data conversion circuits. Complexity versus delay tradeoffs for adder circuits; performance of alternating bit-inversion and carry-lookahead circuits; multipliers. Verilog HDL and FPGA architectures.